JEP184 provides definitions and procedures for characterizing the threshold voltage instability of SiC-based power electronic conversion semiconductor devices having a gate dielectric region biased to turn devices on and off.
Bias Temperature Instabilities (BTI) involve variations of threshold voltage (VT) and other device parameters such as resistance in the on-state and leakage current in the off-state as a function of the stress time, stress voltage, and stress temperature. The assessment of BTI in SiC MOSFETs is particularly challenging since the measured threshold shift can be composed of different components such as long-term VT drift, transient VT changes, and hysteresis behavior or changes in hysteresis. This publication provides guidelines for stress procedures being able to distinguish between different shift components and allowing measurement of their stability over time as affected by gate bias and temperature. JEP184 also closely follows the recent JEDEC publication of JEP183: Guidelines for Measuring the Threshold Voltage (VT) of SiC MOSFETs. Together, these two closely related publications provide the industry much-needed guidance on assessing and evaluating BTI variations of VT, as well as accurately measuring the VT of SiC MOSFETs.
JEDEC Wide Bandgap Power Semiconductor Committee Publishes a Milestone Document for Bias Temperature Instability of Silicon Carbide (SiC) MOS Devices | Business Wire
